1. Field of the Invention
The present invention relates to a semiconductor lead frame, a semiconductor package and a manufacturing method of the semiconductor lead frame and the semiconductor package.
2. Description of the Related Art
Downsizing semiconductor packages has been developed mainly for mobile devices. To achieve this, a variety of CSPs (Chip Scale Package) has been launched to market. Among the CSPs, a semiconductor package as disclosed in Japanese Laid-Open Patent Application Publication No. 11-195742, is expected to be an alternative of FPBGA (Fine Pitch Ball Grid Array) because the semiconductor package has a simple configuration, which can reduce the cost, and can have many pins.
In a method of manufacturing the semiconductor package described in Japanese Laid-Open Patent Application Publication No. 11-195742, a lead frame material made of copper is mainly used as a metal material. A semiconductor lead frame is formed so as to have a semiconductor mounting area and wire bonding parts on one surface (top surface), and connection terminals for external devices opposite to the wire bonding parts on the other surface (back surface). The semiconductor lead frame is completed by partially depositing thin layers by a plating process on the wire bonding parts of one surface (top surface), on a surface opposite to the semiconductor mounting area on the other surface (back surface), and on the connection terminals for external devices corresponding to the opposite surface of the wire bonding parts of the other surface (back surface).
FIG. 13 is a diagram illustrating the conventional method of manufacturing the semiconductor package described in Japanese Laid-Open Patent Application Publication No. 11-195742. As illustrated in FIG. 13, a semiconductor chip 160 is mounted on a lead frame (copper material 110), and then electrodes 161 of the semiconductor chip 160 are connected to wire bonding parts 120 of the lead frame through bonding wires 170. After that, the semiconductor chip 160, the bonding wires 170 and the like are encapsulated in an epoxy resin 180 or the like.
FIG. 14 is a diagram illustrating the conventional method of manufacturing the semiconductor package described in Japanese Laid-Open Patent Application Publication No. 11-195742. As illustrated in FIG. 14, the copper material 110 is etched by using a plating layer 130 as an etching mask, which is formed as a surface of an external connection terminal, thereby electrically separating a semiconductor chip mounting part 114 from an external connection terminal part 115. Finally, the semiconductor device is cut into a size of a semiconductor package, and an individual semiconductor package is completed. Here, etching a metal material from an exposed back surface after encapsulating a top surface of the metal material with an epoxy resin is specifically defined as an etchback, and is hereinafter distinguished from an etching for forming a pattern of a lead frame.
FIG. 15 is a diagram illustrating another conventional method of manufacturing a semiconductor package described in Japanese Laid-Open Patent Application Publication No. 11-195742. As illustrated in FIG. 15, in the method of manufacturing the semiconductor package, the copper material 110 widely used in lead frames is used as a metal material, and the plating layers are formed as the wire bonding parts 120 of one surface (top surface), and plating layers 130 are formed on a surface opposite to a semiconductor mounting area and an external connection terminal surface opposite to the wire bonding parts 120 of the other surface (back surface). After that, a mask made of a resist film is formed on the entire surface of the back surface, and a half etching is performed on the top surface of the copper material 110 up to a predetermined depth by using the formed plating layers 130, thereby completing the semiconductor lead frame. Then, after the semiconductor chip 160 is mounted on the semiconductor lead frame and then electrodes 161 of the semiconductor chip 160 are connected to the wire bonding parts 120 of the semiconductor lead frame through the bonding wires 170, the semiconductor chip 160, the bonding wires 170 and the like are encapsulated in the epoxy resin 180.
FIG. 16 is a diagram illustrating still another conventional method of manufacturing a semiconductor package described in Japanese Laid-Open Patent Application Publication No. 11-195742. As illustrated in FIG. 16, the etchback is performed on the copper material 110 by using the plating layers 130 formed as the external connection terminal surface as an etching mask, and the semiconductor chip mounting part 114 and each of the external connection terminal parts 115 are electrically isolated from each other. Finally, the semiconductor devices are cut into a size of a semiconductor package, thereby completing an individual package.
According to the methods of manufacturing the semiconductor packages described in Japanese Laid-Open Patent Application Publication No. 11-195742, because the terminals (the wire bonding parts and the external connection terminal parts) are connected to each other through the metal material or half-etched remaining portions of the metal material until being encapsulated in the resin, and because the metal material or the half-etched remaining portions of the metal material is removed by an etching after encapsulated in the resin, each of the external connection terminals does not have to be connected to a surrounding frame. Due to this, a supporting part like that provided in the conventional lead frame is not needed, which increases the flexibility of a design, for example, like making it possible to arrange two or more rows of the external connection terminals, and the package size can be reduced while a number of pins can be increased.
However, the semiconductor package illustrated in FIG. 14 has low adhesive strength because the internal terminals, which correspond to the wire bonding parts 120, are held by the encapsulating resin, which corresponds to the epoxy resin 180, only by contacts between the internal terminals and the encapsulating resin. This is likely to cause the internal terminals to drop out of the encapsulating resin while etching the metal material in the etchback process after the resin encapsulation, and to increase costs due to a decrease in process yield. Moreover, the terminals are liable to drop out of the encapsulating resin due to an external shock and the like even after completed as the semiconductor package. To solve this, in the semiconductor package as illustrated in FIGS. 15 and 16 and described in Japanese Laid-Open Patent Application Publication No. 11-195742, the method for increasing the adhesive strength is proposed in which each of the internal terminals is formed into a depressed shape by half-etching the metal material from the top surface, thereby increasing contacting surfaces between the terminals and the encapsulating resin. This semiconductor package can increase the adhesive strength between the terminals and the encapsulating resin by forming each of the internal terminals into the depressed shape, but this method increases the cost because an expensive etching solution needs to be prepared for the half-etching, and the half-etching process needs to be added as an additional process.